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White Electronic Designs
2Mx16 Flash MODULE, SMD 5962-97610
FEATURES
Access Times of 90, 120, 150ns Packaging: * 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207). Fits standard 56 SSOP footprint. * 44 pin Ceramic SOJ (Package 102)** * 44 lead Ceramic Flatpack (Package 208)** Sector Architecture * 32 equal size sectors of 64KBytes each * Any combination of sectors can be erased. Also supports full chip erase. Minimum 100,000 Write/Erase Cycles Minimum Organized as 2Mx16; User Configurable as 2 x 2Mx8 Commercial, Industrial, and Military Temperature Ranges 5 Volt Read and Write. 5V 10% Supply.
WF2M16-XXX5
PRELIMINARY*
Low Power CMOS Data# Polling and Toggle Bit feature for detection of program or erase cycle completion. Supports reading or programming data to a sector not being erased. Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation. RESET# pin resets internal state machine to the read mode. Ready/Busy (RY#/BY#) output for detection of program or erase cycle completion. Multiple Ground Pins for Low Noise Operation
* This product is under development, is not qualified or characterized and is subject to change without notice. ** Package to be developed. Note: For programming information refer to Flash Programming 16M5 Application Notes.
FIGURE 1 - PIN CONFIGURATIONS
WF2M16-XDAX5 56 CSOP TOP VIEW
CS1# A12 A13 A14 A15 NC CS2# NC A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC
WF2M16-XXX5 44 CSOJ (DL)** 44 FLATPACK (FL)** TOP VIEW
CS1# A12 A13 A14 A15 NC CS2# NC A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC
PIN DESCRIPTION
I/O0-15 A0-20 WE# CS1-2# OE# VCC VSS RY/BY# RESET# Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power Supply Ground Ready/Busy Reset
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC #RESET A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 A0 NC NC NC I/O2 I/O10 I/O3 I/O11 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC #RESET A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 A0 NC NC NC I/O2 I/O10 I/O3 I/O11 GND
BLOCK DIAGRAM
I/O0-7 RESET# WE# OE# A0-20 RY / B Y # I/O8-1
2M x 8
2M x 8
** Package to be developed.
CS1# CS2#
NOTE: 1. RY/BY# is an open drain output and should be pulled up to Vcc with an external resistor. 2. Address compatible with Intel 2M8 56 SSOP.
April 2004 Rev. 5
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ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to VSS Power Dissipation Storage Temperature Short Circuit Output Current Data Retention (Mil Temp) Endurance -- write/erase cycles (Mil Temp)
WF2M16-XXX5
PRELIMINARY
CAPACITANCE
(TA = +25C) Unit
V W C mA years cycles
Symbol
VT PT TSTG IOS
Ratings
-2.0 to +7.0 8 -65 to +125 100 20 100,000 min.
Parameter OE# capacitance WE# capacitance CS# capacitance Data I/O capacitance Address input capacitance
Symbol COE CWE CCS CI/O CAD
Conditions Max Unit VIN = 0V, f = 1.0 MHz 25 pF VIN = 0V, f = 1.0 MHz 25 pF VIN = 0V, f = 1.0 MHz 15 pF VI/O = 0V, f = 1.0 MHz 15 pF VIN = 0V, f = 1.0 MHz 25 pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Operating Temperature (Mil.) Operating Temperature (Ind.) Symbol VCC VSS VIH VIL TA TA Min 4.5 0 2.0 -0.5 -55 -40 Typ 5.0 0 - - - - Max 5.5 0 VCC + 0.5 +0.8 +125C +85 Unit V V V V C C
DC CHARACTERISTICS - CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH VLKO Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz CS# = VIL, OE# = VIH VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC 0.3V IOL = 12.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 Min Max 10 10 80 120 4.0 0.45 0.85xVCC 3.2 4.2 Unit A A mA mA mA V V V
NOTES: 1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
April 2004 Rev. 5
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VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Sector Erase (2) Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) RESET# Pulse Width
NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling.
WF2M16-XXX5
PRELIMINARY
AC Characteristics - Write/Erase/Program Operations - WE# Controlled
Symbol tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tWPH Min 90 0 45 0 45 0 45 20 -90 Max Min 120 0 50 0 50 0 50 20 -120 Max Min 150 0 50 0 50 0 50 20 -150 Max ns ns ns ns ns ns ns ns s sec s s sec sec ns ns Unit
300 15 0 50 44 256 tOEH tRP 10 500 10 500 0 50
300 15 0 50 44 256 10 500
300 15
44 256
AC CHARACTERISTICS - READ-ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select High to Output High Z (1) Output Enable High to Output High Z (1) Output Hold from Addresses, CS# or OE# Change, whichever is First RESET# Low to Read Mode (1) 1. Guaranteed by design, not tested.
Symbol Min
TAVAV TAVQV TELQV TGLQV TEHQZ TGHQZ TAXQX TRC TACC TCE TOE TDF TDF TOH TREADY 0 90
-90 Max
90 90 40 20 20 0 20
-120 Min
120 120 120 50 30 30 0 20
-150 Max Min
150 150 150 55 35 35
Unit Max
ns ns ns ns ns ns ns 20 s
April 2004 Rev. 5
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VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter
Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Programming Operation (1) Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) Output Enable Hold Time (4) NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH2 is 1sec. 3. Typical value for Chip Erase Time is 32sec. 4. For Toggle and Data Polling. tOEH 10 tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL 0 44 256 10
WF2M16-XXX5
PRELIMINARY
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
Symbol
tWC tWS tCP tAS tDS tDH tAH tCPH Min 90 0 45 0 45 0 45 20 300 15 0 44 256 10
-90
Max
Min 120 0 50 0 50 0 50 20
-120
Max
Min 150 0 50 0 50 0 50 20
-150
Max
Unit
ns ns ns ns ns ns ns ns
300 15 0
300 15 44 256
s sec s sec sec ns
FIGURE 2 - AC TEST CIRCUIT
AC TEST CONDITIONS
IOL Current Source
D.U.T. CEFF = 50 pf
VZ 1.5V (Bipolar Supply)
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
IOH Current Source
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 y. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit.ATE tester includes jig capacitance.
FIGURE 3 - RESET TIMING DIAGRAM
RESET# tRP tReady
April 2004 Rev. 5
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WF2M16-XXX5
PRELIMINARY
FIGURE 3 - AC WAVEFORMS FOR READ OPERATIONS
tDF
tOH
Addresses Stable
tRC
tOE
tACC
tCE
FDx
FOE#
FWE#
April 2004 Rev. 5
FCS1#/FCS2#
Addresses
5
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Outputs
FDx
High Z
Output Valid
High Z
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WF2M16-XXX5
PRELIMINARY
FIGURE 4 - WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
Data# Polling
OE#
April 2004 Rev. 5
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WE#
CS#
I/O7# I/OOUT
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WF2M16-XXX5
PRELIMINARY
FIGURE 5 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
SA
2AAAH
5555H
2AAAH
5555H
tWPH
tAS
5555H
tWP
AAH FDx tDS
tGHWL
tCS
tDH
55H
tAH
80H
AAH
55H
10H/30H
FWE#
FOE#
Data
NOTE: 1. SA is the sector address for Sector Erase.
April 2004 Rev. 5
FCS1#/FCS2#
Addresses
7
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VCC
tVCS
FAx
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WF2M16-XXX5
PRELIMINARY
FIG. 6 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS
tDF
High Z
D7 = Valid Data
tCH
tOEH
tCE
tWHWH 1 or 2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
tOE
April 2004 Rev. 5
FWE#
FCS#
OE#
8
D0-D6
D7
D0-D6 = Invalid
D7
D0-D7 Valid Data
tOH
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WF2M16-XXX5
PRELIMINARY
FIGURE 7 - ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
Data# Polling
WE#
OE#
NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
April 2004 Rev. 5
9
CS#
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PACKAGE 102: 44 LEAD, CERAMIC SOJ**
WF2M16-XXX5
PRELIMINARY
28.70 (1.13) 0.25 (0.010) 0.2 (0.008) 0.05 (0.002)
3.96 (0.156) MAX 0.89 (0.035) Radius TYP
11.3 (0.446) 0.2 (0.009)
9.55 (0.376) 0.25 (0.010)
1.27 (0.050) 0.25 (0.010)
1.27 (0.050) TYP 26.7 (1.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ** Package to be developed.
PACKAGE 208: 44 LEAD, CERAMIC FLAT PACK**
28.45 (1.120) 0.26 (0.010) 3.18 (0.125) MAX PIN 1 IDENTIFIER
12.95 (0.510) 0.13 (0.005)
9.90 (0.390) 0.13 (0.005)
12.70 (0.500) 0.51 (0.020)
5.08 (0.200) 0.25 (0.010) 0.43 (0.017) 0.05 (0.002) 3.81 (0.150) TYP 32.64 (1.285) TYP 43.17 (1.699) 0.39 (0.015) 1.27 (0.050) TYP 26.67 (1.050) TYP
0.13 (0.005) 0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ** Package to be developed.
April 2004 Rev. 5
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White Electronic Designs
PACKAGE 207: 56 LEAD, CERAMIC SOP*
WF2M16-XXX5
PRELIMINARY
23.63 (0.930) 0.25 (0.010) 21.59 (0.850) TYP 0.18 (0.007) 0.03 (0.001) 3.43 (0.120) 0.38 (0.015) 0.51 (0.020) 0.13 (0.005) 16.13 (0.635) 0.13 (0.005) 12.96 (0.510) 0.15 (0.006) a 0.51 (0.020) 0.13 (0.005) + 1.60 (0.063) TYP PIN 1 IDENTIFIER 0.80 (0.031) TYP 0.25 (0.010) 0.05 (0.002) SEE DETAIL "A" 3.57 (0.140) 0.51 (0.020) 0 / -4 0.51 (0.020) TYP
* Package Dimensions subject to change
DETAIL "A"
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIGURE 8 - ALTERNATE PIN CONFIGURATION FOR WF2M16W-XDAX5
56 CSOP
TOP VIEW
CS1# A12 A13 A14 A15 NC CS2# A21 A20 A19 A18 A17 A16 VCC GND I/O6 I/O14 I/O7 I/O15 RY/BY# OE# WE# NC I/O13 I/O5 I/O12 I/O4 VCC
BLOCK DIAGRAM
NC RESET# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC I/O9 I/O1 I/O8 I/O0 NC NC NC NC I/O2 I/O10 I/O3 I/O11 GND
I/O0-7 RESET# WE# OE# A1-21 RY / B Y # I/O8-15
PIN DESCRIPTION
I/O0-15 A0-21 WE# CS1-2# OE# VCC VSS RY/BY# RESET# Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power Supply Ground Ready/Busy Reset
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
2M x 8
2M x 8
CS1# CS2#
NOTE: 1. RY/BY# is an open drain output and should be pulled up toVcc with an external resistor. 2. Address compatible with Intel 1M16 56 SSOP.
April 2004 Rev. 5
11
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ORDERING INFORMATION
W F 2M16 X - XXX X X 5 X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: Q = Compliant M = Military, 883 Screened I = Industrial C = Commercial
WF2M16-XXX5
PRELIMINARY
-55C to +125C -55C to +125C -40C to +85C 0C to +70C
PACKAGE TYPE: DA = 56 Lead CSOP (Package 207) fits standard 56 SSOP footprint DL = 44 Lead Ceramic SOJ (Package 102)* FL = 44 Lead Ceramic Flatpack (Package 208)* ACCESS TIME (ns) IMPROVEMENT MARK: * Address Pinout for 56 CSOP Package W = Word Wide Applications ORGANIZATION of 2M x 16 User configurable as 2 x 2M x 8 Flash WHITE ELECTRONIC DESIGNS CORP. * Package to be developed.
DEVICE TYPE SECTOR SIZE SPEED
2M x 16 Flash MCP 2M x 16 Flash MCP 2M x 16 Flash MCP 150ns 120ns 90ns
PACKAGE
SMD NO.
5962-97610 04HXX 5962-97610 05HXX 5962-97610 06HXX
April 2004 Rev. 5
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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